1. Technical Field
The invention relates to frequency synthesis with a controlled oscillator incorporated in a phase-locked loop, in which the frequency of the oscillator output signal is divided periodically with mutually different integers, such that the frequency is, on average, divided by a value which is equal to an integer N plus or minus a numerical fraction whose absolute value is smaller than one. The phase position of pulses generated in this way is compared with the phase position of pulses which originate from a reference signal, therewith forming a phase error signal. In order to suppress periodic variations occurring in a control signal to the oscillator due to phase jitter in the loop, there is added to or subtracted from the phase error signal an accumulated correction value which is dependent on said fraction.
2. Prior Art
In practice, it is often not possible to change the frequency in sufficiently small increments in a frequency synthesizer in which the frequency of the output signal is only divided with one single integer for each possible, lockable frequency. This is because the smallest frequency increment or step between two lockable frequencies is equal to the frequency at which phase position comparisons are carried out when generating the phase error signal. Consequently, when small frequency increments are desired, it is necessary to carry out the phase position comparisons at a frequency which is so low that the loop locking time is unacceptably long during the frequency changes.
In the case of a frequency synthesizer in which the output signal frequency is divided periodically with an integer in the manner described in the introduction, the phase position comparisons can be carried out at a frequency which is higher than the smallest increment magnitude during the frequency changes UK Patent Specification 1560233 describes a frequency synthesizer which operates in accordance with this principle. With a frequency synthesizer of this kind, phase jitter occurs in the phase-locked loop due to the fact that the oscillator frequency is divided periodically with a numerical integer, e.g., the numeric values N and N+1. The magnitude of this jitter is at maximum one period of the oscillator output signal, i.e., 2.pi. radians. The maximum jitter is reduced to 2.pi./N of the pulses generated when the frequency of the oscillator signal is divided down. This means that the correction value added to or subtracted from the phase error signal must be multiplied by a factor which is proportional to 1/N. It is difficult in practice, however, to achieve sufficient accuracy in multiplication by the inverted value of N for a number of different integers N.